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That is correct, by default direct gerber export shouldn't produce excellon files as excellon is a different format. Direct gerber export also won't produce ps or png files.
You have two ways getting excellon files:
Note: as of 2019, for the transition time, direct exporting to gerber using any of the old naming styles (e.g. "fixed") will still cross-call the excellon export plugin and produce the extra (non-gerber) drill files. It will also generate a bunch of warnings telling you that this feature will be removed soon. You shouldn't depend on this too much.
Does the padstack has a hole? Does the hole drill through any internal copper layer (in non-thru-hole case)?
Internal copper layers are special: there are multiple of them. The padstack will place the intern shape on any internal copper layer that the padstack's hole reaches. If the padstack has no hole, no internal layer shape is rendered, even if it is specified.
Make sure you have the right layer groups and layers set up:
The DSN format was originally designed for autorouting; an autorouter doesn't need to know the geometry of a hole, assuming copper annulus is always around the hole. Thus old versions of the file format simply does not have a way to describe holes.
Some software extended the format and use a hole directive that pcb-rnd picks up - but if the file does not contain holes, pcb-rnd can't improvise them.
You can use query() to find offending padstacks and use propset() or the padstack editor to install the holes.
The DSN format does not specify silk. There are outline and keepout objects in the format and pcb-rnd loads them on special purpose documentation layers. The use of these objects vary from tool to tool - some tools will draw the bounding box of the part using lines on the outline layer, but other tools may just draw a large, rectangular filled polygon.
Use the per subcircuit layer bindings to map them on a board silk layer.
The DSN format does not specify solder mask or paste. Please use the padstack editor on the affected padstacks.