The silk layer shall have:
Use placement indication graphics sparingly: don't draw full boxes. Either draw two lines on the no-pin sides (e.g. in case of SOT-23-5 or SOIC) or right angle corners of two lines each (e.g. SOT-23-3). The purpose of the silk graphics is to give a slight hint on where a part is located - it is not the assembly layer, it does not need to fully specify the component's shape or bounding box.
The pin 1 indication and refdes text both must be visible after the component is soldered on the board. Placement graphics may be partially hidden by the component. Placement graphics must not extend beyond the courtyard area.
The refdes text must be a text object with the dyntext and floater flags set. The initial position of the refdes text should be outside of the courtyard. Refdes text size should be 100% with pcb-rnd default font, resulting an 'M' height of about 1.2mm.