XSCHEM : schematic capture
and netlisting EDA tool


Xschem is a schematic capture program, it allows creation of hierarchical representation of circuits with a top down approach . By focusing on interfaces, hierarchy and instance properties a complex system can be described in terms of simpler building blocks. A VHDL or Verilog or Spice netlist can be generated from the drawn schematic, allowing the simulation of the circuit. Key feature of the program is its drawing engine written in C and using directly the Xlib drawing primitives; this gives very good speed performance, even on very big circuits. The user interface is built with the Tcl-Tk toolkit, tcl is also the extension language used.

Features


Xschem runs on UNIX systems with X11 and Tcl-Tk toolkit installed.

Project status


date version notes
19980804 0.1 First draft
20040202 1.0 First release
20161203
2.0
Second release, uploading on sourceforge
20200217
2.9.5
2.9.5 release, uploading on repo.hu and sourceforge
20210211
2.9.9
2.9.9 release, skywater 130nm pdk integration
20210911
3.0.0
3.0.0 release, now including windows binary distribution





Documentation

XSCHEM manual

Download Source code

Current release
XSCHEM releases on Sourceforge, without automatic configure
SVN: svn checkout svn://repo.hu/xschem/trunk

Download Windows Binary

Current release

License

The software is released under the GNU GPL, General Public License

Contact

Anyone interested in this project please contact me at the following address:

STEFAN.SCHIPPERS@GMAIL.COM



Software requirements:

- X11
- tcl-tk libs and developent files
- c99 compiler
- bison (only for compiling the grammar parser)
- flex (only for compiling the lexical analyzer
- Xpm library and -dev header files
- awk (tested with gawk and mawk)

Systems tested:

- Linux debian / Redhat
- Solaris sparc
- Windows (with the cygwin layer and cygwin/Xorg X11 server, plus the tcl/tk toolkit and the -dev libraries)



Screenshots

  • analog circuit example

analog circuit
        example

  • digital system for VHDL simulation

dicital example