| ID: | 6313 |
| From: | Gabriel Paubert <pa...@iram.es> |
| Date: | Fri, 26 Jan 2024 18:15:25 +0100 |
| Subject: | Re: [pcb-rnd] padstack local clearance doubling bug (was: Re: |
| in-reply-to: | 6312 from rn...@igor2.repo.hu |
| replies: | 6315 from rn...@igor2.repo.hu |
Hello Igor2, On Fri, Jan 26, 2024 at 02:23:49PM +0100, rnd2@igor2.repo.hu wrote: > Hello Gabriel, >=20 > On Fri, 12 Jan 2024, rnd2@igor2.repo.hu wrote: >=20 > > > > > >On Fri, 12 Jan 2024, Gabriel Paubert wrote: > > > ><snip> > > > >>You can move the via anywhere in the middle of the slot between both > >>power domains and the lower right plane is never clipped. Changing fr= om > >>"no shape" to "no thermal" does not trigger clipping either, while in > >>this case the gap drops down to 50=B5m. > >> > >>At this point, I think the problem has to handed over to you. > > > >as of r38602, it's fixed, please test! > > > >Please note: I've just figured there is a huge design bug, partly=20 > >inherited from geda/pcb^1, a confusion on how clearance value is=20 > >interpreted. > > > >For now: > > > >1. global padstack clearance in file is the size of the gap > > > >2. global padstack clearance in the GUI is the size of the gap > > > >3. local shape clearance in the file is _twice_ the gap > > > >4. local shape clearance in the GUI is _twice_ the gap=20 > > > >I am not yet sure how to fix this as I can't break existing boards. I = will=20 > >probably keep 3 and patch 4 so the UI does the *2 and /2 under the hoo= d so=20 > >it feels like if it was all consistent (you always specify gap when we= say=20 > >"clearance") while we don't need to change the file format, just docum= ent=20 > >the mistake. >=20 >=20 > I've finished working this around: >=20 > - the mistake is documented in the file format doc and code, so it's=20 > official now that we store the double of clearance in the local clearan= ce=20 > field in the file >=20 > - I've modified the padstack proto editor dialog GUI, "second tab", so=20 > that it intenally does the /2 and *2 so the user doesn't see any of thi= s.=20 > In other words: "clearance" in the GUI always means "gap between copper= =20 > and copper". For you this means you no longer need to manually halve th= e=20 > value you enter there. >=20 > - there is no change in the native file format or in the clearance=20 > computation code, so existing boards should not show any change >=20 > - I've found a related bug in the compatibility export helper: if you=20 > saved in some old formats like geda/pcb where there's no padstack but s= md=20 > pad, we used to save local clearance doubled; I've fixed this too. >=20 > All these fixes are available since r38630. >=20 > Gabriel, please test and ACK! Please especially verify that local=20 > clearance on existing boards did not change. >=20 Very lightly tested, but it seems to be more consistent now. Note that there is another place where we typically have to use twice the clearance "but it's only logical": when I create a padstack, I first create the copper layer(s) (most often only the top copper layer since basically everything is SMD these days). Once I'm happy with it (I use a lot of rounded rectangles), I create the soldermask by copying the copper shape and then "grow" it in the "Edit padstack shape" window. Here if I want, say 75=B5m, distance between the copper andthe soldermask= , I have to put 150=B5m in the entry and then click on "Grow". This is not a problem, I'm used to it. It's logical since increasing the width or something by x will increase it on each side by x/2. But it's a kind of clearance for NSMD (non solder mask defined) solder pads. By the way, I have a few pending bugs, which I am unfortunately unable to reproduce: - a minor one is that the silkscreen layer color sometimes changes to the "far side" layer color during long editing sessions and stays that way (the changed color is saved in the file). - another one is a board with a polygon, when I move one corner of the polygon, pcb-rnd crashes on my laptop (Debian) but works most of the time (I think I've seen it crash once or twice) on my work desktop with Ubuntu. Cheers, Gabriel > TIA, >=20 > Igor2
Reply subtree:
6313 Re: [pcb-rnd] padstack local clearance doubling bug (was: Re: from Gabriel Paubert <pa...@iram.es>
6315 Re: [pcb-rnd] padstack local clearance doubling bug (was: Re: Polygon from rn...@igor2.repo.hu