| ID: | 6312 |
| From: | rn...@igor2.repo.hu |
| Date: | Fri, 26 Jan 2024 14:23:49 +0100 (CET) |
| Subject: | [pcb-rnd] padstack local clearance doubling bug (was: Re: Polygon clip bug) |
| in-reply-to: | 6292 from rn...@igor2.repo.hu |
| replies: | 6313 from Gabriel Paubert <pa...@iram.es> |
This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --722076672-1932679302-1706275429=:27953 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Hello Gabriel, On Fri, 12 Jan 2024, rnd2@igor2.repo.hu wrote: > > >On Fri, 12 Jan 2024, Gabriel Paubert wrote: > ><snip> > >>You can move the via anywhere in the middle of the slot between both >>power domains and the lower right plane is never clipped. Changing from >>"no shape" to "no thermal" does not trigger clipping either, while in >>this case the gap drops down to 50µm. >> >>At this point, I think the problem has to handed over to you. > >as of r38602, it's fixed, please test! > >Please note: I've just figured there is a huge design bug, partly >inherited from geda/pcb^1, a confusion on how clearance value is >interpreted. > >For now: > >1. global padstack clearance in file is the size of the gap > >2. global padstack clearance in the GUI is the size of the gap > >3. local shape clearance in the file is _twice_ the gap > >4. local shape clearance in the GUI is _twice_ the gap > >I am not yet sure how to fix this as I can't break existing boards. I will >probably keep 3 and patch 4 so the UI does the *2 and /2 under the hood so >it feels like if it was all consistent (you always specify gap when we say >"clearance") while we don't need to change the file format, just document >the mistake. I've finished working this around: - the mistake is documented in the file format doc and code, so it's official now that we store the double of clearance in the local clearance field in the file - I've modified the padstack proto editor dialog GUI, "second tab", so that it intenally does the /2 and *2 so the user doesn't see any of this. In other words: "clearance" in the GUI always means "gap between copper and copper". For you this means you no longer need to manually halve the value you enter there. - there is no change in the native file format or in the clearance computation code, so existing boards should not show any change - I've found a related bug in the compatibility export helper: if you saved in some old formats like geda/pcb where there's no padstack but smd pad, we used to save local clearance doubled; I've fixed this too. All these fixes are available since r38630. Gabriel, please test and ACK! Please especially verify that local clearance on existing boards did not change. TIA, Igor2 --722076672-1932679302-1706275429=:27953--
Reply subtree:
6312 [pcb-rnd] padstack local clearance doubling bug (was: Re: Polygon clip bug) from rn...@igor2.repo.hu
6313 Re: [pcb-rnd] padstack local clearance doubling bug (was: Re: from Gabriel Paubert <pa...@iram.es>
6315 Re: [pcb-rnd] padstack local clearance doubling bug (was: Re: Polygon from rn...@igor2.repo.hu