| ID: | 6295 |
| From: | rn...@igor2.repo.hu |
| Date: | Sat, 13 Jan 2024 05:12:51 +0100 (CET) |
| Subject: | [pcb-rnd] pcb-rnd custom via placement with local clearance (was: Re: Polygon clip bug) |
| in-reply-to: | 6294 from Gabriel Paubert <pa...@iram.es> |
On Fri, 12 Jan 2024, Gabriel Paubert wrote:
>In this respect there is another slightly irritating feature inherited
>from PCB. You've seen that my default via has different clearances on
>inner and outer layers.
>
>But if I use {F1} to place a via, I get a via with the global clearance
>of the current routing style, overriding the local values. I've learnt
>to live with this and hardly ever use {F1}.
I see. The reason for this is simple:
- local clearance [of the padstack prototype] is used if global clearance
of the [padstack object] instance is 0; (this was invented this way to
keep backward compatibility when I introduced local clearances)
- the instance global clearance is the same clearance field we use for any
other object (lines, arcs, texts)
- there is only one clearance field in the style struct/gui and in the
pen, so when you select a style, the pen takes that one clearance value
and will use it for any new object
- so when you select a style, the style clearance is copied to the pen and
when you place a via (padstack instance) the pen clearance is copied into
he instance [global] clearance; just liek the same style clearance is
inherited by line and arc and text objects
Possible solutions (short and long term, user and coder side):
1. The most trivial user-side workaround
Use 0 clearance for the style, which is probably a terrible idea with your
current config because of newly drawn traces would not clear into polys
(but see solution 3)
2. Another broken workaround
Alternatively you could duplicate your styles, each having a normal
clearance and a 0-clearance variant and then use the 0-clearance variant
for placing the vias. It's really just a theoretical possibility,
switching styles between traces and vias would probably take more clicks
than your current method with off-drawing-area-vias
3. A real user-side solution
Invert the clearance logic!
Since you are doing pro boards, it's very likely you don't have per object
deviations, like "this one line should have a different thickness or
clearance". This is a strenght of pcb-rnd (and pcb) that it allows this,
but in high end application it's rather just a pain.
Lately pcb-rnd allows you to use polygon-side clearances, which means you
specify the clearance value per polygon, not per non-poly object. In
practice it works like this: the final clearance value is either the
object's clearance or the polygon's enforce_clearance, whichever is the
bigger. Polygon's enforce_clearance is 0 by default, so it doesn't
trigger so we are backward compatible.
But you could draw all your polygons with enforce_clearance set to the
_smallest_ clearance you will need on a specific layer and set style
clearances to zero. Then if you for some reason need a larger clearance on
the given layer (e.g. high voltage insulation) you can still do that from
manually setting object clearance to higher.
A major drawback is that style doesn't have a field for
poly enforce_clearance, so you have to set it in propedit after placing
the poly. But nomrally you;d probably have a much smaller number polygons
than traces and vias.
A major limitation: for compatibility reasons: you want to make sure your
object's clearance is not larger than your poly's enforce_clearance so you
set it to some small value, like 1 nanometer. You'd want to set it to 0
for a clean solution, but historically 0 is a special value that makes a
solid connection to the polygon, so you can't do that.
3.a. if you do this for _all_ polygons on all layers, you probably won't
need to use padstack local clearance because you really have per layer
clearance for everything enforced from polygon side; so you could simply
go with object clearances (including padstack global clearance) set to
1nm and no pstk local clearance and achieve the same as now
3.b. or I could implement a config setting that overrides the "0 clearance
is solid conn" rule so you could specify 0 for object clearance and
get pstk local clearance to work and enlarge the minimum clearance
enforceed from the poly; this is needed only if you don't only have
differentclearance per layer but whithin that different clearance per
object type (at least trace vs. pstk).
(Honestly I'd like to avoid 3.b. because this config setting would be too
specialized: it'd be very hard to explain it to users so most probably
only 2..3 users would ever use it and in return it's introducing more
special casings to a place in the code already overloaded with special
casing)
4. coding solution: code side new feature: style and pen
4.a. I could long term add a separate clearance value for padstacks in the
pen and in the style dialog. Plus a checkbox in there to keep it locked to
the common clearance value, because most users will need that. So in this
setup, you would simply put 0 in the padstack clearance in your style,
knowing you will use local clearance anyway.
4.b. Same but add only a single bit that tells the code you want to use
padstack local clearance from that style. On the GUI it's just a checkbox
and an implied padstack clearance 0.
If we go for either of these, we have to wait until lihata board v10
because we need to save this info in the file which requires a file format
change.
5. coding solution: making it easier to do custom via placement
Instead of complicating the style system, we could just introduce an
alternative via placer GUI. It could be a dialog, or rather, just the
board's padstack lib dialog (from the edit menu) with two extra buttons:
- place with style clearance
- place with 0 global clearance
So you would keep that dialog open, it already has all your padstacks
listed in there, with preview, then you'd select the one you want to
place, click the button and you find yourself with the via tool but pen
set up not from style but with your selected padstack plus 0
[global] clearance if you wanted that
This is fairly easy to implement, does not affect the file format, does
not complicate core code. If you like this idea, I could implement it this
weekend.
With your excellent use of the name field in padstack prototypes this
could probably be the best solution for your use case.
Problem: this would set your pen's clearance to 0 so if you go on drawing
lines and arcs, you have a problem. So this would make it easy to switch
to custom via mode, but returning to other tools would also require to
select a style.
6. the hardcore power user solution: solution 5 without the GUI!
I could check whether we have enough actions for this and if not, add the
missing features quickly; imagine an action that:
- picks the padstack proto from the board's proto list, by ID or by name
(that's why I introduced names in the first place!)
- sets it up in your pen
Then you could write a menu patch (either on per user level or even per
project level) and get a submenu somwhere with specific via names,
each invoking this action from above, then setting 0 clearance on pen then
activating the pen tool. You could tear off this menu or make your own
hotkey for each such vias, like {v 1} {v 2}.
This has the same problem of returning to trace drawing as solution 5.
>Actually, it's easier and quicker to keep a few template vias on the
>screen outside the outline of the board and copy them when needed.
>
>For example, in the current 6 layer board I'm finishing (ground on
>layers 1, 5, and 6, and power on layer 2), I keep the following template
>vias:
>- ground, with thermal codes "@nnn@@"
>- power, " @nnn "
>- top to bottom, " nnnn "
>- layer 3 connection " n nn "
>- layer 4 connection " nn n "
Nice workaround!
Best regards,
Igor2
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6295 [pcb-rnd] pcb-rnd custom via placement with local clearance (was: Re: Polygon clip bug) from rn...@igor2.repo.hu