| ID: | 6294 |
| From: | Gabriel Paubert <pa...@iram.es> |
| Date: | Fri, 12 Jan 2024 22:40:21 +0100 |
| Subject: | Re: [pcb-rnd] Polygon clip bug |
| in-reply-to: | 6292 from rn...@igor2.repo.hu |
| replies: | 6295 from rn...@igor2.repo.hu |
Hi Igor2,
On Fri, Jan 12, 2024 at 01:48:19PM +0100, rnd2@igor2.repo.hu wrote:
>=20
>=20
> On Fri, 12 Jan 2024, Gabriel Paubert wrote:
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> <snip>
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> >You can move the via anywhere in the middle of the slot between both
> >power domains and the lower right plane is never clipped. Changing fro=
m
> >"no shape" to "no thermal" does not trigger clipping either, while in
> >this case the gap drops down to 50=B5m.
> >
> >At this point, I think the problem has to handed over to you.
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> as of r38602, it's fixed, please test!
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Fixed as far as I can say.
> Please note: I've just figured there is a huge design bug, partly=20
> inherited from geda/pcb^1, a confusion on how clearance value is=20
> interpreted.
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> For now:
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> 1. global padstack clearance in file is the size of the gap
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> 2. global padstack clearance in the GUI is the size of the gap
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> 3. local shape clearance in the file is _twice_ the gap
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> 4. local shape clearance in the GUI is _twice_ the gap=20
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Yes, I was aware of this. I believe I even sent once a bug report to PCB
about inconsistencies in the clearance definitions but nothing happened.
So I learned to live with this, and believed that you were aware that it
was one of warts of the user interface, but one we can live with.
> I am not yet sure how to fix this as I can't break existing boards. I w=
ill=20
> probably keep 3 and patch 4 so the UI does the *2 and /2 under the hood=
so=20
> it feels like if it was all consistent (you always specify gap when we =
say=20
> "clearance") while we don't need to change the file format, just docume=
nt=20
> the mistake.
Please do.
In this respect there is another slightly irritating feature inherited
from PCB. You've seen that my default via has different clearances on
inner and outer layers.
But if I use {F1} to place a via, I get a via with the global clearance
of the current routing style, overriding the local values. I've learnt
to live with this and hardly ever use {F1}.=20
Actually, it's easier and quicker to keep a few template vias on the
screen outside the outline of the board and copy them when needed.=20
For example, in the current 6 layer board I'm finishing (ground on
layers 1, 5, and 6, and power on layer 2), I keep the following template
vias:
- ground, with thermal codes "@nnn@@"
- power, " @nnn "
- top to bottom, " nnnn "
- layer 3 connection " n nn "
- layer 4 connection " nn n "
I try to avoid "no shape" thermals on external layers. In this
design I never needed anything else (but it's not yet finished).
Best regards,
Gabriel
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>=20
> Footnotes:
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> ^1: original PCB ideas: when you draw a round cap line or arc, and you=20
> need to do a clearance, you simply draw the same line/arc with a larger=
=20
> thickness and subtract that from the poly. This thickness is the origin=
al=20
> thickness plus twice the gap, if you try to specify a "diameter" kind o=
f=20
> thickness (pen diameter you draw with). For some reason the term=20
> "clearance" was used for this larger thickness in the code before I for=
ked=20
> and it leaked into some parts of the padstack shapes because that code=20
> also uses line objects. I should have cleaned this up back in 2017 duri=
ng=20
> the big data model switcover, but I had to keep backward compatibility=20
> back then too and couldn't find a way to make it both compatible and=20
> clean.
I understand.
Reply subtree:
6294 Re: [pcb-rnd] Polygon clip bug from Gabriel Paubert <pa...@iram.es>
6295 [pcb-rnd] pcb-rnd custom via placement with local clearance (was: Re: Polygon clip bug) from rn...@igor2.repo.hu