| ID: | 6292 |
| From: | rn...@igor2.repo.hu |
| Date: | Fri, 12 Jan 2024 13:48:19 +0100 (CET) |
| Subject: | Re: [pcb-rnd] Polygon clip bug |
| in-reply-to: | 6289 from Gabriel Paubert <pa...@iram.es> |
| replies: | 6294 from Gabriel Paubert <pa...@iram.es> , 6312 from rn...@igor2.repo.hu |
This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --722076672-2086583506-1705063699=:27953 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT On Fri, 12 Jan 2024, Gabriel Paubert wrote: <snip> >You can move the via anywhere in the middle of the slot between both >power domains and the lower right plane is never clipped. Changing from >"no shape" to "no thermal" does not trigger clipping either, while in >this case the gap drops down to 50µm. > >At this point, I think the problem has to handed over to you. as of r38602, it's fixed, please test! Please note: I've just figured there is a huge design bug, partly inherited from geda/pcb^1, a confusion on how clearance value is interpreted. For now: 1. global padstack clearance in file is the size of the gap 2. global padstack clearance in the GUI is the size of the gap 3. local shape clearance in the file is _twice_ the gap 4. local shape clearance in the GUI is _twice_ the gap I am not yet sure how to fix this as I can't break existing boards. I will probably keep 3 and patch 4 so the UI does the *2 and /2 under the hood so it feels like if it was all consistent (you always specify gap when we say "clearance") while we don't need to change the file format, just document the mistake. Best regards, Igor2 Footnotes: ^1: original PCB ideas: when you draw a round cap line or arc, and you need to do a clearance, you simply draw the same line/arc with a larger thickness and subtract that from the poly. This thickness is the original thickness plus twice the gap, if you try to specify a "diameter" kind of thickness (pen diameter you draw with). For some reason the term "clearance" was used for this larger thickness in the code before I forked and it leaked into some parts of the padstack shapes because that code also uses line objects. I should have cleaned this up back in 2017 during the big data model switcover, but I had to keep backward compatibility back then too and couldn't find a way to make it both compatible and clean. --722076672-2086583506-1705063699=:27953--
Reply subtree:
6292 Re: [pcb-rnd] Polygon clip bug from rn...@igor2.repo.hu
6294 Re: [pcb-rnd] Polygon clip bug from Gabriel Paubert <pa...@iram.es>
6295 [pcb-rnd] pcb-rnd custom via placement with local clearance (was: Re: Polygon clip bug) from rn...@igor2.repo.hu
6312 [pcb-rnd] padstack local clearance doubling bug (was: Re: Polygon clip bug) from rn...@igor2.repo.hu
6313 Re: [pcb-rnd] padstack local clearance doubling bug (was: Re: from Gabriel Paubert <pa...@iram.es>
6315 Re: [pcb-rnd] padstack local clearance doubling bug (was: Re: Polygon from rn...@igor2.repo.hu