| ID: | 6290 |
| From: | rn...@igor2.repo.hu |
| Date: | Fri, 12 Jan 2024 12:03:51 +0100 (CET) |
| Subject: | Re: [pcb-rnd] Polygon clip bug |
| in-reply-to: | 6289 from Gabriel Paubert <pa...@iram.es> |
| replies: | 6291 from Gabriel Paubert <pa...@iram.es> |
This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --722076672-448732205-1705057431=:27953 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Hi Gabriel, On Fri, 12 Jan 2024, Gabriel Paubert wrote: > > Hi Igor2, > >I've been spending some time (an hour or so) distilling a (hopefully >fairly minimal) test case for a polygon clipping bug I spotted in a medium >size design (~280 components, 4.5MB .rp file size). > >In the attached file, you'll see that the via is not clipped properly on >the right side. The via is my standard via to ground in this design, >with 3 "solid thermals" on layers 1, 5, and 6, and 3 "no shape thermals >on the other layers". Layer 2 is the power distribution layer with >different domains. On the blue Power layer, right? I think I can reproduce it. This one is fortunately not a poly lib bug, but very likely a bbox problem on pcb-rnd-side. I guess the bbox is miscalculated so it doesn't reach the right side poly so there's no attempt to make a clearance. I bet it's a bug related to the noshape feature. I will take a closer look at the code after lunch. >You can move the via anywhere in the middle of the slot between both >power domains and the lower right plane is never clipped. Changing from >"no shape" to "no thermal" does not trigger clipping either, while in >this case the gap drops down to 50µm. > >At this point, I think the problem has to handed over to you. Yup, thanks, very good test case and explanation. >Note that I use different clearances on inner and outer layers, the >reason is that the manufacturer wants larger gaps in the case of "no >shape" (or "hshadow" for pins) vias. This makes sense since the copper >barrel forming the plated hole is larger that the hole so the gap should >be measured from the outer side of the barrel while it is specified from >the hole diameter. Sure! I've seen some IPC recommendation that also used different clearance on outer and inner layer in general. I am really glad to see someone understands and uses these highly obscure and advanced features! >Another discussion worth having in a different thread is how to have DRC >rules which distinguish "no shape" from all the others. If you can distill similar test cases, I'm all ears. I think for the DRC single-layer should be enough most of the time. >And another would be to ask whether a "no shape" thermal should be >considered a valid connection (as far as I can say, it is right now). Same on this topic! Please start separate thread for each. If you are having a deadline and any of these bugs are blocking you, please also indicate that so I can prioritize the bugfix. (This is a generic recommendation, I have a certain freedom in how I allocate time so if you say some bug is really time critical I can often put everything aside and debug it.) For now I assume the first one (poly not clipped) is a blocker, the other two are not. TIA, Igor2 --722076672-448732205-1705057431=:27953--
Reply subtree:
6290 Re: [pcb-rnd] Polygon clip bug from rn...@igor2.repo.hu
6291 Re: [pcb-rnd] Polygon clip bug from Gabriel Paubert <pa...@iram.es>
6293 Re: [pcb-rnd] Polygon clip bug - valgrind from rn...@igor2.repo.hu