| ID: | 6289 |
| From: | Gabriel Paubert <pa...@iram.es> |
| Date: | Fri, 12 Jan 2024 11:34:52 +0100 |
| Subject: | [pcb-rnd] Polygon clip bug |
| replies: | 6290 from rn...@igor2.repo.hu , 6292 from rn...@igor2.repo.hu |
--jI8keyz6grp/JLjh
Content-Type: text/plain; charset=iso-8859-1
Content-Disposition: inline
Content-Transfer-Encoding: quoted-printable
Hi Igor2,
I've been spending some time (an hour or so) distilling a (hopefully
fairly minimal) test case for a polygon clipping bug I spotted in a mediu=
m
size design (~280 components, 4.5MB .rp file size).
In the attached file, you'll see that the via is not clipped properly on
the right side. The via is my standard via to ground in this design,
with 3 "solid thermals" on layers 1, 5, and 6, and 3 "no shape thermals
on the other layers". Layer 2 is the power distribution layer with
different domains.
You can move the via anywhere in the middle of the slot between both
power domains and the lower right plane is never clipped. Changing from
"no shape" to "no thermal" does not trigger clipping either, while in
this case the gap drops down to 50=B5m.
At this point, I think the problem has to handed over to you.
Note that I use different clearances on inner and outer layers, the
reason is that the manufacturer wants larger gaps in the case of "no
shape" (or "hshadow" for pins) vias. This makes sense since the copper
barrel forming the plated hole is larger that the hole so the gap should
be measured from the outer side of the barrel while it is specified from
the hole diameter.
Another discussion worth having in a different thread is how to have DRC
rules which distinguish "no shape" from all the others.
And another would be to ask whether a "no shape" thermal should be
considered a valid connection (as far as I can say, it is right now).
But let us start with this issue.
Regards,
Gabriel
=0A
--jI8keyz6grp/JLjh
Content-Type: text/plain; charset=us-ascii
Content-Disposition: attachment; filename="poly-bug.rp"
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li:styles {
ha:Signal {
via_proto = 0
thickness = 0.15mm
text_thick = 0.0
text_scale = 100
clearance = 0.15mm
}
ha:Power {
via_proto = 0
thickness = 0.2mm
text_thick = 0.0
text_scale = 100
clearance = 0.2mm
}
ha:Fat {
via_proto = 0
thickness = 0.25mm
text_thick = 0.0
text_scale = 100
clearance = 0.2mm
}
ha:Sig-tight {
via_proto = 0
thickness = 0.1mm
text_thick = 0.0
text_scale = 100
clearance = 0.1mm
}
{ha:Internal signals} {
via_proto = 0
thickness = 0.15mm
text_thick = 0.0
text_scale = 100
clearance = 0.2mm
}
}
ha:meta {
ha:size {
y2 = 90.0mm
x1 = 0.0
x2 = 150.0mm
thermal_scale = 0.500000
y1 = 0.0
}
board_name = TEC
ha:grid {
spacing = 0.25mm
offs_x = 0.0
offs_y = 0.0
}
}
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via_proto = 0
text_font_id = 0
text_scale = 100
min_slk = 0.15000000 mm
text_thickness = 0
line_thickness = 150.00 um
poly_isle_area = 10000000000.000000
min_wid = 0.12500000 mm
bloat = 0.12500000 mm
clearance = 200.00 um
}
ha:editor {
wireframe_draw = false
snap_pin = true
live_routing = 0
grid = 250.00 um
hide_names = false
orthogonal_moves = false
all_direction_lines = false
check_planes = 0
line_refraction = 2
show_solder_side = 0
show_drc = true
as_drawn_poly = 0
grid_unit = mm
grids_idx = 10
only_names = 0
highlight_on_point = true
snap_offgrid_line = false
rubber_band_keep_midlinedir = false
buffer_number = 4
lock_names = 0
thin_draw_poly = false
thin_draw = false
rubber_band_mode = true
ha:view {
flip_x = 0
flip_y = 0
}
}
ha:rc {
li:library_search_paths {
?$(rc.path.design)/footprints
}
}
}
}
ha:pixmaps {
}
}
--jI8keyz6grp/JLjh--
Reply subtree:
6289 [pcb-rnd] Polygon clip bug from Gabriel Paubert <pa...@iram.es>
6290 Re: [pcb-rnd] Polygon clip bug from rn...@igor2.repo.hu
6291 Re: [pcb-rnd] Polygon clip bug from Gabriel Paubert <pa...@iram.es>
6293 Re: [pcb-rnd] Polygon clip bug - valgrind from rn...@igor2.repo.hu
6292 Re: [pcb-rnd] Polygon clip bug from rn...@igor2.repo.hu
6294 Re: [pcb-rnd] Polygon clip bug from Gabriel Paubert <pa...@iram.es>
6295 [pcb-rnd] pcb-rnd custom via placement with local clearance (was: Re: Polygon clip bug) from rn...@igor2.repo.hu
6312 [pcb-rnd] padstack local clearance doubling bug (was: Re: Polygon clip bug) from rn...@igor2.repo.hu
6313 Re: [pcb-rnd] padstack local clearance doubling bug (was: Re: from Gabriel Paubert <pa...@iram.es>
6315 Re: [pcb-rnd] padstack local clearance doubling bug (was: Re: Polygon from rn...@igor2.repo.hu