| ID: | 5906 |
| From: | rn...@igor2.repo.hu |
| Date: | Sun, 15 Jan 2023 19:02:25 +0100 (CET) |
| Subject: | Re: [pcb-rnd] wishlist - Automatic Nudge of Refdes |
| in-reply-to: | 5905 from Gabriel Paubert <pa...@iram.es> |
This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --722076672-1857507435-1673805509=:25839 Content-Type: text/plain; CHARSET=UTF-8 Content-Transfer-Encoding: 8BIT Content-ID: <alpine.DEB.2.20.2301151858321.25839@igor2priv> Hello Gabriel, On Sun, 15 Jan 2023, Gabriel Paubert wrote: > Hi Igor2 and Evan, > >Actually in my own library, for most passives (1206 and smaller), I have >the refdes on the assembly layer, since this is what I prefer and need >most of the time. Refdeses on the silkscreen take up far too much space >on the PCB when you have lots and lots of decoupling capacitors, which >is frequent for RF and for high speed logic (FPGAs, etc). I absolutely support that! I was considering writing about this in my original reply, but I thought it was long enough already... But now that you brought it up... Our stock lib is low quality, when measured with today's requirements. It's mostly inherited footprints from geda/pcb's stock lib (heavily cut down), plus the parametrics I designed before the data model switchover, to look similar in style to those old static file footprints. It was nice some 15 years ago, but it's really just 90s stuff. All these static file footprints were drawn back when geda/pcb didn't support drawing on anything else but silk and copper (the outline layer was really a copper layer) and when elements restricted you to have only lines and arcs on silk and one hardwired refdes, always on silk. pcb-rnd has evolved a lot, especially on the data model side. New, modern footprints are very different: - there should be less silk, like the huge frame around so() and dip() are a big waste for dense boards - in parallel there should be much more mechanical drawings on the assy layers, many lines and arcs that really shows how the part would look like, helps a lot in overseeing the placement/orientation, doesn't pollute the silk layer - you can have multiple text objects in a subc, including multiple refdes floaters, and you can easily move them between layers, and on screen we have the red subcircuit virtual layer which shows, on-screen-only the refdes, so you don't even need to put it on any layer if you only want to see it while editing - plus a nice polygon (normally a rectangle) on the keepout layer So yes, another solution, in case you routinely want your silk layer free of refdes text, is to use a better, custom footprint lib that has the refdes text floater on an assy layer. Then when you need refdes on silk, you can move it. (I personally like to have it on silk whenever there's enough room, it helps debugging boards) > >Case in point, look at the layout on an LTC6950 (unfortunately just >obsoleted by Analog): you need 8 decoupling capacitors on one side of >the chip along with 4 differential pairs. Don't try with 0402, only 0201 >fit, and even then I had to use a 50µm grid! Nice example, this kind of dense designs really benefits from modern footprints. >Igor2, I have found a few bugs in pcb-rnd, but I am now very short on >time to distill test cases. No hurry. If you have any of them blocking or extremely annoying, report those, else keep them for later when you have the time. Best regards, Igor2 --722076672-1857507435-1673805509=:25839--
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