| ID: | 5663 |
| From: | rn...@igor2.repo.hu |
| Date: | Wed, 18 May 2022 10:03:14 +0200 (CEST) |
| Subject: | Re: [pcb-rnd] RFC: "design" naming convention |
| in-reply-to: | 5662 from Gabriel Paubert <pa...@iram.es> |
On Wed, 18 May 2022, Gabriel Paubert wrote: > >What you want is a word that describes the content of what goes into a >given top level window, or rather what I'd call its useful or editable >part, no? Yes, but it's also a bit more: it's also a configuration context and some other data. We have a rather flexible configuration system, where you can do per design or per project configuration as well. So in a multi-design setup, when you switch between designs, you also switch between their config contexts. A few trivial examples randomly: - grid settings (not just the current grid size, but also available/preferred grid sizes) - custom drc rules (the per project or per board file variants will play increasingly more important role in a workflow based approach once you can drive them from sch-rnd!) - library paths (which most often would be per project configuration, but you can already have it per board file if you need to, and if we can open multiple files nothing keeps you from opening files of different projects, or open 2 or more full projects) So it's more than just the graphics you see: the design data and configuration and in case of pcb-rnd font data. >Maybe "entity", I'm not completely satisfied with it, but I've not found >anything better. Ok, entity could be a candidate. >For schematics, "page" or "sheet" are fine, but I dislike them for PCB. I agree, these are not really good for PCB. In fact they are good for schematics only if we think in printing, which I usually do not. In a screen-only workflow a page or sheet is not that great for schematics either, especially considering it's more than just the graphics you see. >I think that "item" is too generic, and "part" is not better. >(Maybe I'm biased against "part", because it's what we use at work for a >fully specified component, for example a capacitor of a given value, >combined with package, voltage, and other application dependent >parameters: dielectric type, temperature coefficient, ESR, ESL, >SRF and insertion loss for RF models). I agree, "part" is too overloaded already, same problem as I have with "design" now. Regards, Igor2
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