| ID: | 4355 |
| From: | N <ni...@gmail.com> |
| Date: | Wed, 16 Sep 2020 20:42:29 +0200 |
| Subject: | Re: [pcb-rnd] make YOUR feature request now! (Clerance between |
| in-reply-to: | 4350 from ge...@igor2.repo.hu |
| replies: | 4356 from Bdale Garbee <bd...@gag.com> , 4359 from ge...@igor2.repo.hu |
> >1. Possibility to set clearance distance between nets. > >2. Possibility to set clearance between net classes there nets could be assigned to a voltage class, this is useful then several nets are on same or close enough voltage level considered the same for creepage/clearance distance to other classes or nets. > > There is an important detail about this that decides how we can deal with > these two feature requests. Sort of a clarification I need on them. I can > imagine two contexts for these: > > 1. handle these in DRC checks _after_ editing > > We have two alternative interpreations of them: > > 1.a. pcb-rnd side DRC script, based on network attributes > > The good news: we have all the code for this, it'd take a short drc_query > script to get these checking done based on network attributes. We can > load, save, edit network attributes. We can also import network attributes > when using the tEDAx netlist format. > > The bad news: at the moment I am not aware of any schematics editor that > fills in network attributes. So at the moment you would't be able to > specify your network voltages or clearances in the schematics but you'd > need to edit them in pcb-rnd. In lepton-schematic or gschem it is possible to add attributes on nets but did not think about how to get them end up in netlist before. I am searching the manual for gschem right now, lepton-schematic, backend is implemented in scheme and I have to think very hard then I should edit these kind of files. As importing attributes is not possible for all netlist formats possibility to edit attributes would be good anyway but require more programming. > 1.b. DRC script generated by the schematics editor > > An even more flexible method would be to get your schematics editor > generate DRC rules for ensuring clearances (or whatever other properties) > per network. Get schematic editor to generate DRC rules would without doubt be the best solution. Have seen this before and there it was possible to assign nets to voltage classes and specify clerance between these classes and/or nets, this is very useful in power electronics gate drivers with transistor drain plus a few other component use to jump between rectified positive/negative phase voltage or worse. There is legal requirements on both creeapage and clearance distances, usually above SELV (Safety Extra Low Volgate) of 48 volt. There is usually also need with some extra distance to avoid arcing. Can't imagine it would be very hard to implement a dialog box there it is possible to fill in DRC values although it may take time to get it perfectly designed. To add some references to standards or maybe even values suitable for different voltages and warning for high voltage on help page would also be useful. > In context of gschem, I imagine this would happen in the gnetlist step, in > the tedax exporter: the export script would look at specific attributes > and would decide to create drc checks for them. Yes. May be a good idea to name attribute creepage as this is what it is named in standards then distance is measured on surface of circuit board. To fill number with unit and mayb in mils/inch might be a good idea, example 4mm. > We have everything implemented for this on our side: we can load drc_query > scripts with tEDAx netlists. So this also depends on sch editors exporting > more. > > 2. clearance applied in interactive editing > > Sorry, this is not possible in pcb-rnd, because of a design choice: while > you are editing, pcb-rnd does not know which network you are working for. > This is not a missing feature: this is really a question of decision, how > the whole editing process works, and affectes a lot of things from GUI to > data model. Slightly related I sometimes copy layout and this does not work if layout is assigned to a network. Checking is the most important but mannually entering values is a little bit time consuming. > I know some other software does had a different choice on this. I call > this "tagging vs. free editing" and you can read more on this at: > > http://repo.hu/cgi-bin/pool.cgi?cmd=show&node=net_lab Know about it and used other software. It is not possible to copy layout, have redraw everything. > The two approaches are exclusive, we can't have both. I think it's a value > that pcb-rnd (and it's predecessor, geda/pcb) went for free editing and I > don't plan to change this. Undertand this, pretty sure much time is needed to change this but to fill in clearance values from netlist as is connected to now would be needed. > Ok, that's it in a nutshell. In case you meant context 1, I can write the > DRC scripts probably in this development cycle. If you meant context 2., > then I'm sorry, we can't have this feature. Context 1 DRC to check design is the most important, usually there are rather few distances but easy to miss something. > Best regards, > > Igor2
Reply subtree:
4355 Re: [pcb-rnd] make YOUR feature request now! (Clerance between from N <ni...@gmail.com>
4356 Re: [pcb-rnd] make YOUR feature request now! (Clerance between nets) from Bdale Garbee <bd...@gag.com>
4358 Re: [pcb-rnd] make YOUR feature request now! (Clerance between from ge...@igor2.repo.hu
4359 Re: [pcb-rnd] make YOUR feature request now! (Clerance between from ge...@igor2.repo.hu