| ID: | 3923 |
| From: | ge...@igor2.repo.hu |
| Date: | Sat, 4 Apr 2020 13:58:32 +0200 (CEST) |
| Subject: | Re: [pcb-rnd] drc: Keep board readable warning breaking silk |
| in-reply-to: |
On Sat, 4 Apr 2020, Hannu Vuolasaho wrote: > > On 2.4.2020 18.10, gedau@igor2.repo.hu wrote: >> >> On Thu, 2 Apr 2020, Hannu Vuolasaho wrote: >> >>> Hello! >>> >>> One feature which helps to detect visual problems with boards is to have >>> error >>> on solder mask opening and silk. If this happens, the refdes for example is >>> cut. Holes also break silk >> Thanks, nice one! >> >> Please think over if the following formal definition would work properly >> on positive and negative cases: >> >> "Violation is where a silk object (geometrically) intersects a mask >> object". (Assuming the mask shape of a padstack is treated as a mask >> object for this definition.) > > This is something like Eagle does and I've found it very good indicator of not > thoroughly thought design. I also think this definition went straight to the > target. Thanks, added it to the drc_query TODO (see trunk/doc/TODO.drc_query) <snip> > And mask vs copper which is not so easy but I'll think about it for > completeness sake. Normally you don't want to expose bare FR4, as it is UV and > moisture sensitive. > > UV makes board brittle and moisture inside the board will ruin reflow > soldering. > > However for example LFGA package needs soldermask removing undeneath as the > pins are above the bottom plane while QFN has pins below bottom plane. Outside > those packages look identical, but there is a difference. > > I don't recommend at least as default rule mask vs. copper rule. > > Just for a reminder opening soldermask and exposing (gold plated) copper can be > used in pcb artwork. But please note: copper is copper. If you say mask opening can not be above copper, that means all your smd pads must be covered too. You can try to make an exception for padstacks, but then: - the mask opening is usually bigger than the copper shape, which means it does intersect with copper trace going to the pad, and you don't want that to be an error either - for heavy terminals you use non-padstack objects, which would all be flagged by a padstack based limitation. If you say mask opening can not be above non-copper, then the same story, just inverted (the thin non-copperarea around your padstack copper that is intentionally there). So this could work only if we said something like the percentage of non-copper area under the mask object. Which is rather expensive to calculate (your drc would run for ages doing that for every single terminal!). I am not sure it is worth it. Best regards, Igor2
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3923 Re: [pcb-rnd] drc: Keep board readable warning breaking silk from ge...@igor2.repo.hu