| ID: | 3900 |
| From: | ge...@igor2.repo.hu |
| Date: | Fri, 3 Apr 2020 09:05:55 +0200 (CEST) |
| Subject: | Re: [pcb-rnd] connectivity bug -> fullpoly again |
| in-reply-to: | 3843 from ge...@igor2.repo.hu |
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Hello Britton,
On Mon, 16 Mar 2020, gedau@igor2.repo.hu wrote:
>On Sun, 15 Mar 2020, Britton Kerin wrote:
>>
>>pcb version 4.2.0 exhibits the same behavior.
>
<snip>
>Now we have two independent bugs about this:
>
>bug#1: if you {c f} on either half of the cut polygon in my example
>file, you sill see the other half is marked too. This is clearly wrong, as
>there's no connection between the two parts.
<snip>
(This didn't change now.)
>
>bug#2: there's always a 'first island', which is the only island for the
>non-fullpoly polygon (which is the largest area island in that case). In
>the fullpoly case, there may be further islands. Most of the code, like
>the connectivity code will unfortunately look only for the first islandd
>(which can be considered as a bug we want to fix).
I've fixed this one as of r30353. Please test and ACK.
Attached is an extended test case that has one overlapping object of each
relevant object type on the second island (on the top) of a cut-in-half
fullpoly. With the older/buggy version of pcb-rnd these objects won't
connect with {c f}, with the fixed version they will.
However, because of the more dangerous bug#1 still lurking in our code
with no much chance for a fix, I maintain this:
>Do not ever use the fullpoly flag. That simple. That feature is and always
>has been just broken [by] design.
<snip>
>V. long temr solution, developer side
>
>The fullpoly flag is a dangerous thing that should not be used by users
>and should be removed from the code. In fact I should just remove it
>imediately - except that I can't because it would break compatibility with
>the obsolete pcb format....
>
>So the plan is this:
<snip>
>4. [...] I will look at whether I canfix bug#2 for cheap. If yes, I will
>probably do that. [...]
This is what happened now. The fix won't introduce major slowdown in the
find code (rats nest optimization and drc) and is not too large either so
I decided to go for it.
Rationale: we generally want to get rid of fullpoly and we won't want new
design to use it. But we will need to load old design properly, even if we
will have bug#1 on fullpolys probably forever.
Regards,
Igor2
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3900 Re: [pcb-rnd] connectivity bug -> fullpoly again from ge...@igor2.repo.hu