| ID: | 3682 |
| From: | ge...@igor2.repo.hu |
| Date: | Wed, 15 Jan 2020 05:05:16 +0100 (CET) |
| Subject: | Re: [pcb-rnd] DRC annular ring issue |
| in-reply-to: | 3680 from pc...@cuvoodoo.info |
| replies: | 3684 from pc...@cuvoodoo.info |
This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --0-1757111433-1579061116=:2358 Content-Type: TEXT/PLAIN; charset=US-ASCII On Tue, 14 Jan 2020, pcb-rnd@cuvoodoo.info wrote: >maybe this is a PEBKAC, but when I run a DRC on the following board, it complains the annular ring it too small. >the minimum should be 0.6 mm, but the measured is 0.0 mm. >the DRC rules and via setting (for Signals) are both 0.6 mm ring. >I can't reproduce the issue on a new/empty design with only a via. >here the design I get this issue for: >https://tsaitgaist.info/private/usb-c_receptacle_breakout.lht Flagging that via as a DRC error is not a bug - that via really violates the drc settings you have on that board. It's probably a misunderstanding of the related config settings (we may need to refine the description the conf node descriptions). Minimal test case attached (took your board and removed everything but the offending via). For the board fab, the outer diameter of your via does not matter: it's just a copper shape, like any line or polygon. What matters is the tickness of the remaining ring, after drilling. This still could be handled by the usual minimum trace thickness, but some fabs tend to have a requirement of thicker via rings because drilling may have a tolerance on positioning or could eat away a bit more copper for tool wear, vibrations, or other mechanical factors. So when you set "minimum annular ring", you are setting the minimum remaining copper thickness at the "neck" of your padstack. In your concentric round via, this is easy to calculate: (copper_dia - hole_dia) / 2 If you have non-concentric padstack (most usual case is oblong through-hole pad with a drilled hole, like home made boards for those those old DIP packages), the code goes and tries to find the neck, where the hole is the closest to the outer contour of the padstack shape, on any layer, and the minimum is checked there. What I did on drc-good.lht was simply applying the above formula and calculate the DRC requirement for your specific via: (0.6 - 0.3) / 2 = 0.15mm (So your via is like a copper trace ring of 0.15mm around the hole). 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3682 Re: [pcb-rnd] DRC annular ring issue from ge...@igor2.repo.hu
3684 Re: [pcb-rnd] DRC annular ring issue from pc...@cuvoodoo.info
3685 Re: [pcb-rnd] DRC annular ring issue from ge...@igor2.repo.hu