| ID: | 3448 |
| From: | Bob Paddock <bo...@gmail.com> |
| Date: | Sun, 13 Oct 2019 10:38:41 -0400 |
| Subject: | Re: [pcb-rnd] COT data model (was: non-graphical schematics, layout) |
| in-reply-to: | 3445 from Mychaela Falconia <my...@gmail.com> |
| replies: | 3450 from Mychaela Falconia <my...@gmail.com> |
On Sun, Oct 13, 2019 at 5:36 AM Mychaela Falconia <mychaela.falconia@gmail.com> wrote: > For example, the circuit has plenty of bypass caps to GND, and > for each of these caps the GND pad is "drowned" in the GND pour, > whereas the signal (non-GND) pad has a clearance around it. I hope that is not as literal as it sounds. If that means no thermal relief on the GND side then that can to lead to soldering problems and tombstoning. Tombstoning can happen when there is not equal thermal mass on both pads.
Reply subtree:
3448 Re: [pcb-rnd] COT data model (was: non-graphical schematics, layout) from Bob Paddock <bo...@gmail.com>
3450 Re: [pcb-rnd] COT data model (was: non-graphical schematics, layout) from Mychaela Falconia <my...@gmail.com>
3451 Re: [pcb-rnd] COT data model (was: non-graphical schematics, layout) from Bob Paddock <bo...@gmail.com>