pcb-rnd knowledge pool

DRC: typical use cases

drc_typical by Tibor 'Igor2' Palinkas on 2021-05-20	Tags: howto, drc
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Abstract: Every production board should be ran through the Design Rule Checker (DRC) before sent to the fab house. This pool node lists and explains typical and practical use cases for the new DRC system, serving both as guideline and checklist.

Every netlisted board: copper

Make sure to set the value for $min_copper_overlap and $min_copper_clearance (this is the minimum clearance the fab house specified in its offer). These control how shorts and broken nets are checked for.

Note: the DRC does not run logical connectivity check, it focuses on geometry. So the final check should always be:

optimize rats net (hotkey: {c r})
look at the log to see if every net is completed
run the DRC

Every board: editing mistakes

The beyond_drawing_area stock rule will detect stray objects beyond the drawing area. Normally any such object should be removed - export will not truncate the output at drawing area edges!

No board shall use the FULLPOLY flag (that feature is semi-obsolete and is rather dangerous). The stock DRC rule called fullpoly will list polygons that have the flag and feature multiple islands. Remove those polygons and redraw them as multiple, non-full polygons.

If the invalid_polygons rule lists any polygon, fix it, even if it looks good. Self intersecting polygons are always broken and keeping them without cleaning them up will risk export, other DRC operations and connection finding.

Every board: part collision

The ko_named stock rule can ensure there is no mechanical collision between parts on the board. This requires a doc layer set up for the purpose and that every single footprint specify that part's courtyard. Unfortunately as of 2021, stock footprints and majority of edakrill footprints don't have courtyard, so this feature works best if you maintain your own footprint lib.

Every board: fabbing details

Set $min_drill - every fab offer will specify the smallest hole diameter they are willing to drill and the stock hole_dia rule can catch holes that are accidentally smaller.

Watch for violations coming from hole_overlap. Some fab houses will not like overlapping drilled holes. In that case either move the padstacks further apart or use a slot instead of two holes.

Set $min_copper_thickness; this is similar to the minimum drill diameter in that it is specified by the fab house offer. Some fab houses will also specify minimum silk width, which should be put in $min_silk_thickness.

Because of drilling positional precision, copper "rings" of vias and through-hole pins have a minimum thickness so a slightly misaligned drill won't break the ring. The DRC can check this by looking at smallest neck of each padstack. The stock rule for this uses $min_ring.

High speed digital boards

There's a DRC script available for finding floating copper objects that are not connected to any network.

For microstrip lines there is an optional DRC script that can estimate trace impedance object by object using rule-of-thumb formula (no simulation involved).

If some critical nets should be kept short, or pairs or groups of nets should be kept at the same length, the netlen script can be used to set absolute or relative length targets per net.

Beside matched length, another rule-of-thumb for pairs or groups of parallel digital nets is to have the same number of vias so the parasitics are the same, which can be checked using the netvianum DRC script.

For the net based rules, best practice is when these net attributes are set on the schematics and are imported using the tEDAx netlist format.

High voltage or high current nets

High current networks need more copper, which is typically implemented as thicker traces. The tracewidth DRC script can verify that.

For high voltage networks a per net clearance can be verified using the netclr DRC script.

An alternative is to require higher clearance value on a specific region of the board. This can be done using the drc_zone_clr DRC script. Regions are drawn using polygons on a doc layer.